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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_ISAR3, Instruction Set Attribute Register 3</h1><p>The ID_ISAR3 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the instruction sets implemented by the PE in AArch32 state.</p>

      
        <p>Must be interpreted with <a href="AArch32-id_isar0.html">ID_ISAR0</a>, <a href="AArch32-id_isar1.html">ID_ISAR1</a>, <a href="AArch32-id_isar2.html">ID_ISAR2</a>, <a href="AArch32-id_isar4.html">ID_ISAR4</a>, and <a href="AArch32-id_isar5.html">ID_ISAR5</a>. </p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_ISAR3 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_isar3_el1.html">ID_ISAR3_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_ISAR3 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_ISAR3 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">T32EE</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">TrueNOP</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">T32Copy</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">TabBranch</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">SynchPrim</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">SVC</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">SIMD</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">Saturate</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">T32EE, bits [31:28]</h4><div class="field">
      <p>Indicates the implemented T32EE instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>T32EE</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the ENTERX and LEAVEX instructions, and modifies the load behavior to include null checking.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0000</span>.</p></div><h4 id="fieldset_0-27_24">TrueNOP, bits [27:24]</h4><div class="field">
      <p>Indicates the implemented true NOP instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>TrueNOP</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented. This means there are no NOP instructions that do not have any register dependencies.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds true NOP instructions in both the T32 and A32 instruction sets. This also permits additional NOP-compatible hints.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-23_20">T32Copy, bits [23:20]</h4><div class="field">
      <p>Indicates the support for T32 non flag-setting MOV instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>T32Copy</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not supported. This means that in the T32 instruction set, encoding T1 of the MOV (register) instruction does not support a copy from a low register to a low register.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds support for T32 instruction set encoding T1 of the MOV (register) instruction, copying from a low register to a low register.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-19_16">TabBranch, bits [19:16]</h4><div class="field">
      <p>Indicates the implemented Table Branch instructions in the T32 instruction set. Defined values are:</p>
    <table class="valuetable"><tr><th>TabBranch</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the TBB and TBH instructions.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-15_12">SynchPrim, bits [15:12]</h4><div class="field">
      <p>Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>SynchPrim</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>If SynchPrim_frac == <span class="binarynumber">0b000</span>, no Synchronization Primitives implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td><p>If SynchPrim_frac == <span class="binarynumber">0b000</span>, adds the LDREX and STREX instructions.</p>
<p>If SynchPrim_frac == <span class="binarynumber">0b011</span>, also adds the CLREX, LDREXB, STREXB, and STREXH instructions.</p></td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>If SynchPrim_frac == <span class="binarynumber">0b000</span>, as for [<span class="binarynumber">0b001</span>, <span class="binarynumber">0b011</span>] and also adds the LDREXD and STREXD instructions.</p>
        </td></tr></table><p>All other combinations of SynchPrim and SynchPrim_frac are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-11_8">SVC, bits [11:8]</h4><div class="field">
      <p>Indicates the implemented SVC instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>SVC</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>Not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the SVC instruction.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-7_4">SIMD, bits [7:4]</h4><div class="field">
      <p>Indicates the implemented SIMD instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>SIMD</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the SSAT and USAT instructions, and the Q bit in the PSRs.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>As for <span class="binarynumber">0b0001</span>, and adds the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0011</span>.</p>
<p>The SIMD field relates only to implemented instructions that perform SIMD operations on the general-purpose registers. In an implementation that supports Advanced SIMD and floating-point instructions, <a href="AArch32-mvfr0.html">MVFR0</a>, <a href="AArch32-mvfr1.html">MVFR1</a>, and <a href="AArch32-mvfr2.html">MVFR2</a> give information about the implemented Advanced SIMD instructions.</p></div><h4 id="fieldset_0-3_0">Saturate, bits [3:0]</h4><div class="field">
      <p>Indicates the implemented Saturate instructions. Defined values are:</p>
    <table class="valuetable"><tr><th>Saturate</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>None implemented. This means no non-Advanced SIMD saturate instructions are implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>Adds the QADD, QDADD, QDSUB, and QSUB instructions, and the Q bit in the PSRs.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><div class="access_mechanisms"><h2>Accessing ID_ISAR3</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0010</td><td>0b011</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_ISAR3;
elsif PSTATE.EL == EL2 then
    R[t] = ID_ISAR3;
elsif PSTATE.EL == EL3 then
    R[t] = ID_ISAR3;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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